A 32nm CMOS all-digital reconfigurable fractional frequency divider for LO generation in multistandard SoC radios with on-the-fly interference management

A VCO used in a PLL inside a wireless transceiver can be sensitive to interference from other radio circuitry (e.g. on-chip PA), components of the SoC system (e.g. clocks and their harmonics) and nearby radios. To prevent VCO pulling by the PA, fractional dividers can be used to offset the VCO frequency (fVCO) with respect to the PA. Multistandard radios covering, for example, WiFi 2.4 to 2.5GHz and 5 to 5.8GHz, and WiMAX 2.3 to 2.7GHz and 3.3 to 3.8GHz, may require multiple VCOs and/or multiple fractional dividers to cover all bands [1], resulting in complexity and area overhead. This paper proposes a versatile reconfigurable fractional divider capable of covering the above standards with a single VCO with 20% tuning range. The divider is all-digital, hence scaling-friendly, and uses digital calibration to eliminate the need for filtering and area-intensive inductors. The versatility afforded by the reconfigurable fractional divider allows for the transceiver's LO generation (LOG) frequency plan to be adjusted on-the-fly. This can avoid VCO pulling from interferers which may not be known a-priori, like SoC-CPU clocks that are adjusted dynamically for best performance.