A low power subband video decoder architecture

The paper describes a VLSI architecture designed to reconstruct a subband-encoded video stream. This architecture differs from previous designs in its low power operation. The chip operates at a maximum 20 MHz with a 1.5 V supply and can process up to 10 M color (YUV) pixels/sec while dissipating only 16 mW. The low power consumption is achieved through efficient algorithm-to-hardware mapping, a low-complexity subband filter, minimal memory accesses, a reduced supply voltage, and elimination of external memory support. A single chip will support color images up to 352 pixels wide, while multiple chip configurations can achieve any desired display resolution.<>