Geyser-2:第二个具有细粒度运行时功率门控的原型CPU

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011) Pub Date : 2011-01-25 DOI:10.1109/ASPDAC.2011.5722310

Lei Zhao, D. Ikebuchi, Yoshiki Saito, M. Kamata, N. Seki, Y. Kojima, H. Amano, S. Koyama, T. Hashida, Y. Umahashi, D. Masuda, K. Usami, K. Kimura, M. Namiki, S. Takeda, Hiroshi Nakamura, Masaaki Kondo

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引用次数: 13

摘要

Geyser-2是第二个原型MIPS CPU，它提供了一个由指令控制的细粒度运行时功率门控(PG)。Geyser-1[1]，第一个原型只提供细粒度的运行时PG核心。虽然它在实际芯片上展示了泄漏功率的降低，但由于I/O速度的限制，工作频率限制在60MHz。Geyser-2的缓存和TLB机制的实现表明:(1)运行时PG至少可以在嵌入式系统常用的200MHz时钟下工作;(2)它在具有操作系统的实际应用程序环境下也是高效的。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Geyser-2: The second prototype CPU with fine-grained run-time power gating

Geyser-2 is the second prototype MIPS CPU which provides a fine-grained run-time power gating (PG) controlled by instructions. Geyser-1[1], the first prototype only provides the fine-grained run-time PG core. Although it demonstrated the leakage power reduction on a real chip, the operational frequency is limited at 60MHz because of the limitation of the I/O speed. Geyser-2 with cache and TLB mechanism is implemented to show (1) run-time PG works at least with 200MHz which is commonly used clock for embedded systems, and (2) it is also efficient on the environment with real application programs with an operating system.

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16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)

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