{"title":"减少冗余功率处理的高效PFC稳压器","authors":"M. Chow, C. Tse, Yim-Shu Lee","doi":"10.1109/PESC.1999.788985","DOIUrl":null,"url":null,"abstract":"Conventional PFC power supplies employ two cascading stages that deal separately with PFC and voltage regulation. Since power is processed serially by two power stages, the efficiency is limited. In this paper a PFC power supply with improved efficiency is proposed. This circuit makes use of a parallel configuration that reduces unnecessary processing of all power by two stages serially. The circuit is derived from consideration of the power flow between the input, the load and the storage capacitor. A specific circuit implementation is described and the test results are reported.","PeriodicalId":292317,"journal":{"name":"30th Annual IEEE Power Electronics Specialists Conference. Record. (Cat. No.99CH36321)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"22","resultStr":"{\"title\":\"An efficient PFC voltage regulator with reduced redundant power processing\",\"authors\":\"M. Chow, C. Tse, Yim-Shu Lee\",\"doi\":\"10.1109/PESC.1999.788985\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Conventional PFC power supplies employ two cascading stages that deal separately with PFC and voltage regulation. Since power is processed serially by two power stages, the efficiency is limited. In this paper a PFC power supply with improved efficiency is proposed. This circuit makes use of a parallel configuration that reduces unnecessary processing of all power by two stages serially. The circuit is derived from consideration of the power flow between the input, the load and the storage capacitor. A specific circuit implementation is described and the test results are reported.\",\"PeriodicalId\":292317,\"journal\":{\"name\":\"30th Annual IEEE Power Electronics Specialists Conference. Record. (Cat. No.99CH36321)\",\"volume\":\"35 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1999-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"22\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"30th Annual IEEE Power Electronics Specialists Conference. Record. (Cat. No.99CH36321)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/PESC.1999.788985\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"30th Annual IEEE Power Electronics Specialists Conference. Record. (Cat. No.99CH36321)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/PESC.1999.788985","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An efficient PFC voltage regulator with reduced redundant power processing
Conventional PFC power supplies employ two cascading stages that deal separately with PFC and voltage regulation. Since power is processed serially by two power stages, the efficiency is limited. In this paper a PFC power supply with improved efficiency is proposed. This circuit makes use of a parallel configuration that reduces unnecessary processing of all power by two stages serially. The circuit is derived from consideration of the power flow between the input, the load and the storage capacitor. A specific circuit implementation is described and the test results are reported.
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