VLSI浮点单元中移位器、乘法器和除法器的实现

1987 IEEE 8th Symposium on Computer Arithmetic (ARITH) Pub Date : 1987-05-18 DOI:10.1109/ARITH.1987.6158711

V. Peng, S. Samudrala, M. Gavrielov

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引用次数: 14

摘要

对VLSI浮点单元的组合移位器、乘法器和除法器的几种实现方案进行了介绍和比较。比较是在单芯片实现的背景下进行的，考虑到目前可用的MOS技术所施加的限制。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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On the implementation of shifters, multipliers, and dividers in VLSI floating point units

Several options for the implementation of combinatorial shifters, multipliers, and dividers for a VLSI floating point unit are presented and compared. The comparisons are made in the context of a single chip implementation in light of the constraints imposed by currently available MOS technology.

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1987 IEEE 8th Symposium on Computer Arithmetic (ARITH)

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