Computer aided test synthesis for a parallel scan design of finite state sequential machines

A parallel scan design for finite-state machines (FSMs) was proposed by S.M. Reddy and R. Dandapani (1987), and analyzed for critical parameters such as area, delay, and active devices. The authors study the design presented by Reddy and Dandapani for test parameters including increase in test vectors for both cross-point and single stuck-at faults, fault coverage, and time taken for fault detection. It is shown that even though there is an increase in the number of test vectors due to additional hardware, the testing time is reduced to the parallelism of the design. NMOS technology is used in the analysis.<>