{"title":"FPGA中的组合分频器","authors":"J. Kolouch","doi":"10.1109/RADIOELEK.2007.371427","DOIUrl":null,"url":null,"abstract":"The possibility of synthesis of combinational divider for unsigned integer numbers in FPGA devices is considered with respect to recent technology development. Three VHDL models are discussed, and corresponding synthesis and implementation results - resource consumption and propagation delay, together with the bit width limitation, are compared.","PeriodicalId":446406,"journal":{"name":"2007 17th International Conference Radioelektronika","volume":"31 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Combinational Divider in FPGA\",\"authors\":\"J. Kolouch\",\"doi\":\"10.1109/RADIOELEK.2007.371427\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The possibility of synthesis of combinational divider for unsigned integer numbers in FPGA devices is considered with respect to recent technology development. Three VHDL models are discussed, and corresponding synthesis and implementation results - resource consumption and propagation delay, together with the bit width limitation, are compared.\",\"PeriodicalId\":446406,\"journal\":{\"name\":\"2007 17th International Conference Radioelektronika\",\"volume\":\"31 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-04-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 17th International Conference Radioelektronika\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RADIOELEK.2007.371427\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 17th International Conference Radioelektronika","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RADIOELEK.2007.371427","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The possibility of synthesis of combinational divider for unsigned integer numbers in FPGA devices is considered with respect to recent technology development. Three VHDL models are discussed, and corresponding synthesis and implementation results - resource consumption and propagation delay, together with the bit width limitation, are compared.
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