Design and Simulation of 90 nm Threshold Logic Carry-Look-Ahead Adder

Addition is one of the most important operations in microprocessors and digital signal processing systems. Different adder architectures have been proposed in the literature. One of the most widely used architectures is the Carry-Look-Ahead (CLA) which is known for its high speed. In this paper, we present a CLA adder design using Threshold Logic Gates (TLG) instead of conventional logic gates. The adder was designed in 90nm CMOS technology, with wired-inverters TLGs. Moreover, a transistor-level power reduction technique was applied to all TLGs that comprise the adder.