便携式应用中效率84%的20mhz DC-DC降压转换器的设计

A. Maity, A. Patra, N. Yamamura, J. Knight
{"title":"便携式应用中效率84%的20mhz DC-DC降压转换器的设计","authors":"A. Maity, A. Patra, N. Yamamura, J. Knight","doi":"10.1109/VLSID.2011.37","DOIUrl":null,"url":null,"abstract":"This paper presents the design and implementation of a 20 MHz voltage mode DC-DC buck converter with high power efficiency. The power efficiency has been improved by minimising the short circuit current in the driver stage. At the same time, a high gain, wide-band error amplifier topology with reduced current consumption, improves various dynamic performance parameters such as settling time, load and line regulations of the converter. A prototype of a 20 MHz DCDC buck converter is implemented and fabricated in 0.5 ?m Bi-CMOS process with a maximum of 600 mA load current driving capability in the input voltage range of 2.7-5.5 V which is suitable for single-cell lithiumion (Li-Ion) battery operated portable applications. A reasonably good settling time of 10 ?s is observed in the measured result with off-chip filter components of L=270 nH, C=1.6 ?F. The measured value of load regulation and line regulation are 1.6 mV/A and 3 mV/V respectively. A maximum of 84% power efficiency is achieved at 2.7 V to 1.2 V conversion. A very low form factor of 2.5 mm× 2.5 mm× 0.7 mm, has been achieved by using power power flip-chip packaging technology.","PeriodicalId":371062,"journal":{"name":"2011 24th Internatioal Conference on VLSI Design","volume":"59 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-01-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"33","resultStr":"{\"title\":\"Design of a 20 MHz DC-DC Buck Converter with 84 Percent Efficiency for Portable Applications\",\"authors\":\"A. Maity, A. Patra, N. Yamamura, J. Knight\",\"doi\":\"10.1109/VLSID.2011.37\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents the design and implementation of a 20 MHz voltage mode DC-DC buck converter with high power efficiency. The power efficiency has been improved by minimising the short circuit current in the driver stage. At the same time, a high gain, wide-band error amplifier topology with reduced current consumption, improves various dynamic performance parameters such as settling time, load and line regulations of the converter. A prototype of a 20 MHz DCDC buck converter is implemented and fabricated in 0.5 ?m Bi-CMOS process with a maximum of 600 mA load current driving capability in the input voltage range of 2.7-5.5 V which is suitable for single-cell lithiumion (Li-Ion) battery operated portable applications. A reasonably good settling time of 10 ?s is observed in the measured result with off-chip filter components of L=270 nH, C=1.6 ?F. The measured value of load regulation and line regulation are 1.6 mV/A and 3 mV/V respectively. A maximum of 84% power efficiency is achieved at 2.7 V to 1.2 V conversion. A very low form factor of 2.5 mm× 2.5 mm× 0.7 mm, has been achieved by using power power flip-chip packaging technology.\",\"PeriodicalId\":371062,\"journal\":{\"name\":\"2011 24th Internatioal Conference on VLSI Design\",\"volume\":\"59 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-01-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"33\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 24th Internatioal Conference on VLSI Design\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSID.2011.37\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 24th Internatioal Conference on VLSI Design","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSID.2011.37","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 33

摘要

本文设计并实现了一种高功率效率的20mhz电压型DC-DC降压变换器。通过最小化驱动阶段的短路电流,功率效率得到了提高。同时,高增益、宽频带误差放大器拓扑结构降低了电流消耗,改善了变换器的各种动态性能参数,如稳定时间、负载和线路调节。采用0.5 μ m Bi-CMOS工艺制作了20 MHz DCDC降压变换器原型,在2.7-5.5 V输入电压范围内具有最大600 mA负载电流驱动能力,适用于单电池锂离子(Li-Ion)电池供电的便携式应用。在片外滤波元件L=270 nH, C=1.6 F时,测量结果显示沉淀时间为10 s。负载调节和线路调节的测量值分别为1.6 mV/A和3 mV/V。在2.7 V到1.2 V转换时,功率效率最高可达84%。采用功率倒装芯片封装技术,实现了2.5 mm× 2.5 mm× 0.7 mm的极低外形尺寸。
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Design of a 20 MHz DC-DC Buck Converter with 84 Percent Efficiency for Portable Applications
This paper presents the design and implementation of a 20 MHz voltage mode DC-DC buck converter with high power efficiency. The power efficiency has been improved by minimising the short circuit current in the driver stage. At the same time, a high gain, wide-band error amplifier topology with reduced current consumption, improves various dynamic performance parameters such as settling time, load and line regulations of the converter. A prototype of a 20 MHz DCDC buck converter is implemented and fabricated in 0.5 ?m Bi-CMOS process with a maximum of 600 mA load current driving capability in the input voltage range of 2.7-5.5 V which is suitable for single-cell lithiumion (Li-Ion) battery operated portable applications. A reasonably good settling time of 10 ?s is observed in the measured result with off-chip filter components of L=270 nH, C=1.6 ?F. The measured value of load regulation and line regulation are 1.6 mV/A and 3 mV/V respectively. A maximum of 84% power efficiency is achieved at 2.7 V to 1.2 V conversion. A very low form factor of 2.5 mm× 2.5 mm× 0.7 mm, has been achieved by using power power flip-chip packaging technology.
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