Navneet Kaur, N. Gupta, Hitesh Pahuja, Balwinder Singh, S. Panday
{"title":"基于低功耗FinFET的10T SRAM单元","authors":"Navneet Kaur, N. Gupta, Hitesh Pahuja, Balwinder Singh, S. Panday","doi":"10.1109/CIPECH.2016.7918772","DOIUrl":null,"url":null,"abstract":"Memory occupies more than 70 percent of area in today's system on chip and the trends continue to be increases in coming years. As the technology is scaling the bulk MOSFET faces various challenges which lead to increased leakage. Below 32nm technology, FinFET is the most promising substitute to bulk CMOS technology because of reduced short channel effect. The proposed 10T SRAM cell is designed using MOSFET, FinFET at 16nm technology node and its performance parameters such as power, delay, Power Delay Product (PDP), leakage current and Static Noise Margin (SNM) are compared with conventional 6T SRAM cell.","PeriodicalId":247543,"journal":{"name":"2016 Second International Innovative Applications of Computational Intelligence on Power, Energy and Controls with their Impact on Humanity (CIPECH)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"Low Power FinFET based 10T SRAM cell\",\"authors\":\"Navneet Kaur, N. Gupta, Hitesh Pahuja, Balwinder Singh, S. Panday\",\"doi\":\"10.1109/CIPECH.2016.7918772\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Memory occupies more than 70 percent of area in today's system on chip and the trends continue to be increases in coming years. As the technology is scaling the bulk MOSFET faces various challenges which lead to increased leakage. Below 32nm technology, FinFET is the most promising substitute to bulk CMOS technology because of reduced short channel effect. The proposed 10T SRAM cell is designed using MOSFET, FinFET at 16nm technology node and its performance parameters such as power, delay, Power Delay Product (PDP), leakage current and Static Noise Margin (SNM) are compared with conventional 6T SRAM cell.\",\"PeriodicalId\":247543,\"journal\":{\"name\":\"2016 Second International Innovative Applications of Computational Intelligence on Power, Energy and Controls with their Impact on Humanity (CIPECH)\",\"volume\":\"10 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 Second International Innovative Applications of Computational Intelligence on Power, Energy and Controls with their Impact on Humanity (CIPECH)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CIPECH.2016.7918772\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 Second International Innovative Applications of Computational Intelligence on Power, Energy and Controls with their Impact on Humanity (CIPECH)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CIPECH.2016.7918772","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Memory occupies more than 70 percent of area in today's system on chip and the trends continue to be increases in coming years. As the technology is scaling the bulk MOSFET faces various challenges which lead to increased leakage. Below 32nm technology, FinFET is the most promising substitute to bulk CMOS technology because of reduced short channel effect. The proposed 10T SRAM cell is designed using MOSFET, FinFET at 16nm technology node and its performance parameters such as power, delay, Power Delay Product (PDP), leakage current and Static Noise Margin (SNM) are compared with conventional 6T SRAM cell.
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