{"title":"一种新的数模转换电阻串结构","authors":"P.K. Oborn, D. Comer","doi":"10.1109/ASIC.1997.617026","DOIUrl":null,"url":null,"abstract":"This paper introduces a resistor string architecture for implementing a digital to analog converter on a CMOS circuit process. The proposed circuit maintains the advantages of guaranteed monotonicity inherent in previous resistor string architectures but provides a higher efficiency of resistor usage. Using \"virtual resistance coding\" it is possible to obtain a very high integral and differential linearities (/spl sim/0% LSB). Likewise, this DAC architecture requires only one buffer amplifier, offering potential high-speed operation.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"A new digital to analog converter resistor string architecture\",\"authors\":\"P.K. Oborn, D. Comer\",\"doi\":\"10.1109/ASIC.1997.617026\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper introduces a resistor string architecture for implementing a digital to analog converter on a CMOS circuit process. The proposed circuit maintains the advantages of guaranteed monotonicity inherent in previous resistor string architectures but provides a higher efficiency of resistor usage. Using \\\"virtual resistance coding\\\" it is possible to obtain a very high integral and differential linearities (/spl sim/0% LSB). Likewise, this DAC architecture requires only one buffer amplifier, offering potential high-speed operation.\",\"PeriodicalId\":300310,\"journal\":{\"name\":\"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)\",\"volume\":\"33 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-09-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASIC.1997.617026\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASIC.1997.617026","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A new digital to analog converter resistor string architecture
This paper introduces a resistor string architecture for implementing a digital to analog converter on a CMOS circuit process. The proposed circuit maintains the advantages of guaranteed monotonicity inherent in previous resistor string architectures but provides a higher efficiency of resistor usage. Using "virtual resistance coding" it is possible to obtain a very high integral and differential linearities (/spl sim/0% LSB). Likewise, this DAC architecture requires only one buffer amplifier, offering potential high-speed operation.
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