{"title":"了解并发错误检测超标量微体系结构的性能","authors":"Jared C. Smolens, Jangwoo Kim, J. Hoe, B. Falsafi","doi":"10.1109/ISSPIT.2005.1577062","DOIUrl":null,"url":null,"abstract":"Superscalar out-of-order micro architectures can be modified to support redundant execution of a program as two concurrent threads for soft-error detection. However, the extra workload from redundant execution incurs a performance penalty due to increased contention for resources throughout the datapath. We present four key parameters that affect performance of these designs, namely 1) issue and functional unit bandwidth, 2) issue queue and reorder buffer capacity, 3) decode and retirement bandwidth, and 4) coupling between redundant threads' instantaneous resource requirements. We then survey existing work in concurrent error detecting superscalar micro architectures and evaluate these proposals with respect to the four factors","PeriodicalId":421826,"journal":{"name":"Proceedings of the Fifth IEEE International Symposium on Signal Processing and Information Technology, 2005.","volume":"136 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-12-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Understanding the performance of concurrent error detecting superscalar microarchitectures\",\"authors\":\"Jared C. Smolens, Jangwoo Kim, J. Hoe, B. Falsafi\",\"doi\":\"10.1109/ISSPIT.2005.1577062\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Superscalar out-of-order micro architectures can be modified to support redundant execution of a program as two concurrent threads for soft-error detection. However, the extra workload from redundant execution incurs a performance penalty due to increased contention for resources throughout the datapath. We present four key parameters that affect performance of these designs, namely 1) issue and functional unit bandwidth, 2) issue queue and reorder buffer capacity, 3) decode and retirement bandwidth, and 4) coupling between redundant threads' instantaneous resource requirements. We then survey existing work in concurrent error detecting superscalar micro architectures and evaluate these proposals with respect to the four factors\",\"PeriodicalId\":421826,\"journal\":{\"name\":\"Proceedings of the Fifth IEEE International Symposium on Signal Processing and Information Technology, 2005.\",\"volume\":\"136 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-12-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the Fifth IEEE International Symposium on Signal Processing and Information Technology, 2005.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSPIT.2005.1577062\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the Fifth IEEE International Symposium on Signal Processing and Information Technology, 2005.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSPIT.2005.1577062","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Understanding the performance of concurrent error detecting superscalar microarchitectures
Superscalar out-of-order micro architectures can be modified to support redundant execution of a program as two concurrent threads for soft-error detection. However, the extra workload from redundant execution incurs a performance penalty due to increased contention for resources throughout the datapath. We present four key parameters that affect performance of these designs, namely 1) issue and functional unit bandwidth, 2) issue queue and reorder buffer capacity, 3) decode and retirement bandwidth, and 4) coupling between redundant threads' instantaneous resource requirements. We then survey existing work in concurrent error detecting superscalar micro architectures and evaluate these proposals with respect to the four factors