半自定义电压岛技术及其在高速串行链路中的应用[CMOS有功功率降低]

J. Carballo, J. Burns, Seung-Moon Yoo, I. Vo, V. R. Norman
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引用次数: 2

摘要

降低电源电压是降低CMOS有功功率的一种已知技术。我们提出了一种基于内部调节和选择性定制设计的半定制电压岛方法。这种方法可以实现透明嵌入,因为不需要额外的外部电源。我们将该方法应用于高速串行链路,并通过有针对性地应用定制电路和逻辑设计来保持高性能。在一个3000门3.2 Gbps多协议串行链路接收逻辑核心上对该方法进行了测试。当电源从1.2 V降低到0.95 V时,芯片显示功耗节省超过25%。
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A semi-custom voltage-island technique and its application to high-speed serial links [CMOS active power reduction]
Supply-voltage reduction is a known technique for reducing CMOS active power. We propose a semi-custom voltage-island approach based on internal regulation and selective custom design. This approach enables transparent embedding, since no additional external power supply is needed. We apply the approach to high-speed serial links, and we show that high performance is retained through targeted application of custom circuit and logic design. A chip is presented that evaluates the presented approach on a 3000 gate 3.2 Gbps multi-protocol serial-link receiver logic core. When reducing the supply from 1.2 V to 0.95 V, the chip demonstrates power savings of over 25%.
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Voltage scheduling under unpredictabilities: a risk management paradigm [logic design] Uncertainty-based scheduling: energy-efficient ordering for tasks with variable execution time [processor scheduling] Level conversion for dual-supply systems [low power logic IC design] A selective filter-bank TLB system [embedded processor MMU for low power] A semi-custom voltage-island technique and its application to high-speed serial links [CMOS active power reduction]
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