M. Coppola, R. Locatelli, G. Maruccia, L. Pieralisi, A. Scandurra
{"title":"Spidergon:一种新型片上通信网络","authors":"M. Coppola, R. Locatelli, G. Maruccia, L. Pieralisi, A. Scandurra","doi":"10.1109/ISSOC.2004.1411133","DOIUrl":null,"url":null,"abstract":"Summary form only given. The SoC (System on Chip) design demands for novel architectural and circuital solutions to cope with the global wires issue, pushing the on-chip communication as a crucial and precious resource. In the context of the communication centric paradigm and according to a layered based design, it is foreseen that current on-chip shared bus will be, at least partially, replaced by a micronetwork interconnection implementing a flexible packet-based communication (A. Jantsch and H. Tenhunen, \"Networks on Chip\", Kluwer Academic Publishers, 2003). We state that the availability of an efficient on-chip communication platform is one of the most important enabling factors for the development of efficient and cost effective multi processor SoC in the near and long-term future. This summary presents the low cost, high performance on-chip communication network, called Spidergon, developed by the AST (Advanced System Technology) of STMicroelectronics as the possible evolution of STBus technology.","PeriodicalId":268122,"journal":{"name":"2004 International Symposium on System-on-Chip, 2004. Proceedings.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"209","resultStr":"{\"title\":\"Spidergon: a novel on-chip communication network\",\"authors\":\"M. Coppola, R. Locatelli, G. Maruccia, L. Pieralisi, A. Scandurra\",\"doi\":\"10.1109/ISSOC.2004.1411133\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Summary form only given. The SoC (System on Chip) design demands for novel architectural and circuital solutions to cope with the global wires issue, pushing the on-chip communication as a crucial and precious resource. In the context of the communication centric paradigm and according to a layered based design, it is foreseen that current on-chip shared bus will be, at least partially, replaced by a micronetwork interconnection implementing a flexible packet-based communication (A. Jantsch and H. Tenhunen, \\\"Networks on Chip\\\", Kluwer Academic Publishers, 2003). We state that the availability of an efficient on-chip communication platform is one of the most important enabling factors for the development of efficient and cost effective multi processor SoC in the near and long-term future. This summary presents the low cost, high performance on-chip communication network, called Spidergon, developed by the AST (Advanced System Technology) of STMicroelectronics as the possible evolution of STBus technology.\",\"PeriodicalId\":268122,\"journal\":{\"name\":\"2004 International Symposium on System-on-Chip, 2004. Proceedings.\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-11-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"209\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2004 International Symposium on System-on-Chip, 2004. Proceedings.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSOC.2004.1411133\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2004 International Symposium on System-on-Chip, 2004. Proceedings.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSOC.2004.1411133","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Summary form only given. The SoC (System on Chip) design demands for novel architectural and circuital solutions to cope with the global wires issue, pushing the on-chip communication as a crucial and precious resource. In the context of the communication centric paradigm and according to a layered based design, it is foreseen that current on-chip shared bus will be, at least partially, replaced by a micronetwork interconnection implementing a flexible packet-based communication (A. Jantsch and H. Tenhunen, "Networks on Chip", Kluwer Academic Publishers, 2003). We state that the availability of an efficient on-chip communication platform is one of the most important enabling factors for the development of efficient and cost effective multi processor SoC in the near and long-term future. This summary presents the low cost, high performance on-chip communication network, called Spidergon, developed by the AST (Advanced System Technology) of STMicroelectronics as the possible evolution of STBus technology.