{"title":"可重复使用的1GHz超标量ARM处理器的设计","authors":"Stephen Hill","doi":"10.1109/HOTCHIPS.2006.7477864","DOIUrl":null,"url":null,"abstract":"This article consists of a collection of slides from the author's conference presentation on the design of a reusable 1GHz, superscalar ARM processor. Some of the specific topics discussed include: an overview of the ARM Cortex-A8 Tiger processor; a comparison of reusability verys redeployability; significance to the Cortex-A8 processor; the effects on design flow and microarchitecture; and the interaction of energy efficiency and reusable design.","PeriodicalId":302249,"journal":{"name":"2006 IEEE Hot Chips 18 Symposium (HCS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Design of a reusable 1GHz, superscalar ARM processor\",\"authors\":\"Stephen Hill\",\"doi\":\"10.1109/HOTCHIPS.2006.7477864\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This article consists of a collection of slides from the author's conference presentation on the design of a reusable 1GHz, superscalar ARM processor. Some of the specific topics discussed include: an overview of the ARM Cortex-A8 Tiger processor; a comparison of reusability verys redeployability; significance to the Cortex-A8 processor; the effects on design flow and microarchitecture; and the interaction of energy efficiency and reusable design.\",\"PeriodicalId\":302249,\"journal\":{\"name\":\"2006 IEEE Hot Chips 18 Symposium (HCS)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-08-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 IEEE Hot Chips 18 Symposium (HCS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/HOTCHIPS.2006.7477864\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 IEEE Hot Chips 18 Symposium (HCS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/HOTCHIPS.2006.7477864","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design of a reusable 1GHz, superscalar ARM processor
This article consists of a collection of slides from the author's conference presentation on the design of a reusable 1GHz, superscalar ARM processor. Some of the specific topics discussed include: an overview of the ARM Cortex-A8 Tiger processor; a comparison of reusability verys redeployability; significance to the Cortex-A8 processor; the effects on design flow and microarchitecture; and the interaction of energy efficiency and reusable design.
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