{"title":"基于最小奇异值阈值的MIMO系统高效高吞吐量球体解码器的FPGA实现","authors":"Xiang Wu, J. Thompson","doi":"10.1109/AHS.2010.5546236","DOIUrl":null,"url":null,"abstract":"In this paper, we present an efficient high-throughput threshold based sphere decoder (TSD) for multiple-input multiple-output (MIMO) systems. Depending on the instantaneous channel conditions, the proposed TSD compares the smallest singular value of the channel matrix with a predefined threshold on a frame-by-frame basis and switches between full expansion (FE) and partial expansion (PE) for the tree traversal to accelerate the detection procedure. The TSD has been implemented and validated on an FPGA platform and results indicate that the proposed decoder is very suitable for a highly-parallel and fully-pipelined hardware implementation. The proposed algorithm offers considerable throughput improvement over the original fixed-complexity sphere decoder (FSD) with only slightly increased resource use.","PeriodicalId":101655,"journal":{"name":"2010 NASA/ESA Conference on Adaptive Hardware and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"FPGA implementation of an efficient high-throughput sphere decoder for MIMO systems based on the smallest singular value threshold\",\"authors\":\"Xiang Wu, J. Thompson\",\"doi\":\"10.1109/AHS.2010.5546236\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we present an efficient high-throughput threshold based sphere decoder (TSD) for multiple-input multiple-output (MIMO) systems. Depending on the instantaneous channel conditions, the proposed TSD compares the smallest singular value of the channel matrix with a predefined threshold on a frame-by-frame basis and switches between full expansion (FE) and partial expansion (PE) for the tree traversal to accelerate the detection procedure. The TSD has been implemented and validated on an FPGA platform and results indicate that the proposed decoder is very suitable for a highly-parallel and fully-pipelined hardware implementation. The proposed algorithm offers considerable throughput improvement over the original fixed-complexity sphere decoder (FSD) with only slightly increased resource use.\",\"PeriodicalId\":101655,\"journal\":{\"name\":\"2010 NASA/ESA Conference on Adaptive Hardware and Systems\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-06-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 NASA/ESA Conference on Adaptive Hardware and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/AHS.2010.5546236\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 NASA/ESA Conference on Adaptive Hardware and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/AHS.2010.5546236","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
FPGA implementation of an efficient high-throughput sphere decoder for MIMO systems based on the smallest singular value threshold
In this paper, we present an efficient high-throughput threshold based sphere decoder (TSD) for multiple-input multiple-output (MIMO) systems. Depending on the instantaneous channel conditions, the proposed TSD compares the smallest singular value of the channel matrix with a predefined threshold on a frame-by-frame basis and switches between full expansion (FE) and partial expansion (PE) for the tree traversal to accelerate the detection procedure. The TSD has been implemented and validated on an FPGA platform and results indicate that the proposed decoder is very suitable for a highly-parallel and fully-pipelined hardware implementation. The proposed algorithm offers considerable throughput improvement over the original fixed-complexity sphere decoder (FSD) with only slightly increased resource use.