{"title":"椭圆曲线处理器GLV方法的FPGA实现","authors":"Mark Hamilton, W. Marnane","doi":"10.1109/ReConFig.2009.66","DOIUrl":null,"url":null,"abstract":"This paper outlines a FPGA implementation of an elliptic curve processor that utilises the GLV method. The GLV method has been shown to be able to speed up computationally expensive point multiplication operations. We also present an implementation of a Hiasat multiplier which can be used with special moduli to further speed up point multiplications. The Hiasat multiplier takes advantage of fast reduction techniques that can be applied to Mersenne primes. The results are then compared with standard multiplication algorithms.","PeriodicalId":325631,"journal":{"name":"2009 International Conference on Reconfigurable Computing and FPGAs","volume":"39 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":"{\"title\":\"FPGA Implementation of an Elliptic Curve Processor Using the GLV Method\",\"authors\":\"Mark Hamilton, W. Marnane\",\"doi\":\"10.1109/ReConFig.2009.66\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper outlines a FPGA implementation of an elliptic curve processor that utilises the GLV method. The GLV method has been shown to be able to speed up computationally expensive point multiplication operations. We also present an implementation of a Hiasat multiplier which can be used with special moduli to further speed up point multiplications. The Hiasat multiplier takes advantage of fast reduction techniques that can be applied to Mersenne primes. The results are then compared with standard multiplication algorithms.\",\"PeriodicalId\":325631,\"journal\":{\"name\":\"2009 International Conference on Reconfigurable Computing and FPGAs\",\"volume\":\"39 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-12-09\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"11\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 International Conference on Reconfigurable Computing and FPGAs\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ReConFig.2009.66\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 International Conference on Reconfigurable Computing and FPGAs","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ReConFig.2009.66","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
FPGA Implementation of an Elliptic Curve Processor Using the GLV Method
This paper outlines a FPGA implementation of an elliptic curve processor that utilises the GLV method. The GLV method has been shown to be able to speed up computationally expensive point multiplication operations. We also present an implementation of a Hiasat multiplier which can be used with special moduli to further speed up point multiplications. The Hiasat multiplier takes advantage of fast reduction techniques that can be applied to Mersenne primes. The results are then compared with standard multiplication algorithms.