{"title":"验证一个32位的RISC处理器核心","authors":"Tuukka Kasanko, J. Nurmi","doi":"10.1109/ISSOC.2004.1411161","DOIUrl":null,"url":null,"abstract":"Verification is currently the most time consuming task in the development of new designs. Automation must be introduced in order to achieve satisfactory results within reasonable time. This work presents how verification was conducted for one SoC component, a 32-bit RISC processor core. A wide variety of tools and methods were used in the process.","PeriodicalId":268122,"journal":{"name":"2004 International Symposium on System-on-Chip, 2004. Proceedings.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Verification of a 32-bit RISC processor core\",\"authors\":\"Tuukka Kasanko, J. Nurmi\",\"doi\":\"10.1109/ISSOC.2004.1411161\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Verification is currently the most time consuming task in the development of new designs. Automation must be introduced in order to achieve satisfactory results within reasonable time. This work presents how verification was conducted for one SoC component, a 32-bit RISC processor core. A wide variety of tools and methods were used in the process.\",\"PeriodicalId\":268122,\"journal\":{\"name\":\"2004 International Symposium on System-on-Chip, 2004. Proceedings.\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-11-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2004 International Symposium on System-on-Chip, 2004. Proceedings.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSOC.2004.1411161\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2004 International Symposium on System-on-Chip, 2004. Proceedings.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSOC.2004.1411161","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Verification is currently the most time consuming task in the development of new designs. Automation must be introduced in order to achieve satisfactory results within reasonable time. This work presents how verification was conducted for one SoC component, a 32-bit RISC processor core. A wide variety of tools and methods were used in the process.