{"title":"高速DCT/IDCT使用流水线CORDIC算法","authors":"Feng Zhou, Peter Kornerup","doi":"10.1109/ARITH.1995.465361","DOIUrl":null,"url":null,"abstract":"This paper describes DCT (IDCT) computations using the CORDIC algorithm. By rewriting the DCT, for a 1/spl times/8 DCT only 6 CORDIC computations are needed, whereas a 1/spl times/16 DCT requires 22 CORDIC computations. But these can all be pipelined through a single CORDIC unit, so 16/spl times/16 DCT's becomes feasible for HDTV compression. Only some simple adders, registers and a more complicated carry look-ahead adder are needed, end the computing speed can be very high. Limited only by the delay of a carry look-ahead adder, the delay time of the pipelined structure is 2-10 ns and the data rate as 100-500 MHz for an 8/spl times/8 DCT/IDCT and 72.2-366.6 MHz for a 16/spl times/16 DCT/IDCT when using two units.<<ETX>>","PeriodicalId":332829,"journal":{"name":"Proceedings of the 12th Symposium on Computer Arithmetic","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"1995-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"18","resultStr":"{\"title\":\"High speed DCT/IDCT using a pipelined CORDIC algorithm\",\"authors\":\"Feng Zhou, Peter Kornerup\",\"doi\":\"10.1109/ARITH.1995.465361\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes DCT (IDCT) computations using the CORDIC algorithm. By rewriting the DCT, for a 1/spl times/8 DCT only 6 CORDIC computations are needed, whereas a 1/spl times/16 DCT requires 22 CORDIC computations. But these can all be pipelined through a single CORDIC unit, so 16/spl times/16 DCT's becomes feasible for HDTV compression. Only some simple adders, registers and a more complicated carry look-ahead adder are needed, end the computing speed can be very high. Limited only by the delay of a carry look-ahead adder, the delay time of the pipelined structure is 2-10 ns and the data rate as 100-500 MHz for an 8/spl times/8 DCT/IDCT and 72.2-366.6 MHz for a 16/spl times/16 DCT/IDCT when using two units.<<ETX>>\",\"PeriodicalId\":332829,\"journal\":{\"name\":\"Proceedings of the 12th Symposium on Computer Arithmetic\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-07-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"18\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 12th Symposium on Computer Arithmetic\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ARITH.1995.465361\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 12th Symposium on Computer Arithmetic","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ARITH.1995.465361","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
High speed DCT/IDCT using a pipelined CORDIC algorithm
This paper describes DCT (IDCT) computations using the CORDIC algorithm. By rewriting the DCT, for a 1/spl times/8 DCT only 6 CORDIC computations are needed, whereas a 1/spl times/16 DCT requires 22 CORDIC computations. But these can all be pipelined through a single CORDIC unit, so 16/spl times/16 DCT's becomes feasible for HDTV compression. Only some simple adders, registers and a more complicated carry look-ahead adder are needed, end the computing speed can be very high. Limited only by the delay of a carry look-ahead adder, the delay time of the pipelined structure is 2-10 ns and the data rate as 100-500 MHz for an 8/spl times/8 DCT/IDCT and 72.2-366.6 MHz for a 16/spl times/16 DCT/IDCT when using two units.<>