{"title":"嵌入式DRAM开发和应用中的问题","authors":"D. Keitel-Schulz, N. Wehn","doi":"10.1109/ISSS.1998.730592","DOIUrl":null,"url":null,"abstract":"After being niche markets for several years, application markets for one-chip integration of large DRAMs and logic circuits are growing very rapidly as the transition to 0.25 /spl mu/m technologies will offer customers up to 128 Mbit of embedded DRAM and 500 Kgates logic. However embedded DRAM implies many technical challenges to be solved. In this paper we will address some of these technical issues in more detail.","PeriodicalId":305333,"journal":{"name":"Proceedings. 11th International Symposium on System Synthesis (Cat. No.98EX210)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1998-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"14","resultStr":"{\"title\":\"Issues in embedded DRAM development and applications\",\"authors\":\"D. Keitel-Schulz, N. Wehn\",\"doi\":\"10.1109/ISSS.1998.730592\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"After being niche markets for several years, application markets for one-chip integration of large DRAMs and logic circuits are growing very rapidly as the transition to 0.25 /spl mu/m technologies will offer customers up to 128 Mbit of embedded DRAM and 500 Kgates logic. However embedded DRAM implies many technical challenges to be solved. In this paper we will address some of these technical issues in more detail.\",\"PeriodicalId\":305333,\"journal\":{\"name\":\"Proceedings. 11th International Symposium on System Synthesis (Cat. No.98EX210)\",\"volume\":\"6 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1998-12-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"14\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings. 11th International Symposium on System Synthesis (Cat. No.98EX210)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSS.1998.730592\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. 11th International Symposium on System Synthesis (Cat. No.98EX210)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSS.1998.730592","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Issues in embedded DRAM development and applications
After being niche markets for several years, application markets for one-chip integration of large DRAMs and logic circuits are growing very rapidly as the transition to 0.25 /spl mu/m technologies will offer customers up to 128 Mbit of embedded DRAM and 500 Kgates logic. However embedded DRAM implies many technical challenges to be solved. In this paper we will address some of these technical issues in more detail.
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