Step Response Detection Technique for Self-Calibrating Predistortion GFSK ΣΔ Modulation Loops

A novel calibration scheme for predistortion SigmaDelta PLLs is proposed in this paper. In contrast to present calibration algorithms this technique detects the integral phase variation of the loops step response. The architecture uses minimum chip area by synchronously sampling the data content of an delay locked loop. Using this technique to detect the phase difference during a step response allows to determine the real loop gain within 7 mus with an accuracy better than 0.1%. Obtaining this, the deviation from the desired loop gain can be adjusted by a digitally controlled charge pump in order to derive the wanted loop transfer function. This is mandatory for predistortion modulation loops