An MTCMOS Subthreshold-Leakage Reduction Algorithm

CMOS circuits that contain multiple branches in the pull-down network (PDN) suffer from the trade-off between the leakage-power reduction and the improvement of the propagation delay. As a solution, multiple threshold voltages can be used in order to reduce the subthreshold leakage in some paths while maintaining the speed requirement in others. In this paper, a novel multiple threshold-voltage CMOS (MTCMOS) subthreshold-leakage reduction algorithm is presented that optimizes the design of CMOS circuits with several branches in the PDN. Specifically, the threshold voltages of certain devices in the PDN are increased in order to reduce the subthreshold leakage while keeping the current-driving capabilities of these devices within certain limits in order not to degrade the performance. Simulation results using the 45 nm CMOS technology confirms this reduction with no speed penalty.