Optimizing carry-lookahead logic through a comparison of PMOS and NMOS block inversions

The fast performance of a carry-lookahead adder (CLA) comes from the ability to input a carry signal into each full adder block that depends on all preceding adder blocks. While the translation of this carry signal logic into CMOS transistors has a unique solution, this paper demonstrates that there are four different ways to connect the PMOS and NMOS transistors to Vdd, ground, and the output. Each method is analyzed according to its speed performance to find the most desirable CMOS configuration. This configuration is further improved through transistor sizing to achieve the most optimized CLA carry circuit. The result is given as a schematic, as well as a stick diagram.