Low power tri-state register files design for modern out-of-order processors

In this paper, we propose a novel integrated circuit and architectural level technique to reduce power consumption of register files in high-performance microprocessors. Our simulation results on 32-nm process show 12.7–14.1% power reduction for ROB (Reorder Buffer)-based microprocessors and 12.4–17.9% power reduction for checkpoint-based microprocessors, respectively, with less than 5% impact on excess time.