Hardware implementation of the FAPEC lossless data compressor for space

The instruments used in modern space missions require increasing amounts of telemetry resources to download the acquired data to the ground. Data compression helps to mitigate this problem and, therefore, it is currently seen as a mandatory stage for most of the missions, although the available on-board processing power is often modest. In many cases, data compression must be performed without losses. FAPEC is a lossless data compression algorithm that typically offers better ratios than the CCSDS 121.0 recommendation on realistic data sets. Its compression efficiency is higher than 90% of the Shannon limit in most cases, even in presence of large amounts of noise and outliers. FAPEC has been successfully implemented in software and its low-complexity algorithm also seemed suitable for a hardware implementation. In this paper we describe a prototype FPGA implementation which has been developed targeting the antifuse radiation-hardened RTAX Actel family. We have assessed that FAPEC can be easily implemented in hardware without requiring an external memory. The prototype presents an initial throughput of 32 Mbit/s and a complexity of 120 Kgate, hence being a compact and a robust solution for generic lossless compression. Finally, we discuss potential improvements that could easily boost the performance beyond the barrier of 100 Mbit/s.