{"title":"单模复数ALU的实现","authors":"R.-S. Kao, F. Taylor","doi":"10.1109/ARITH.1987.6158703","DOIUrl":null,"url":null,"abstract":"Recently the complex residue number system, or RNS, has been a subject of intense study. One special embodiment of this theory is the single modulus complex RNS processor which suggests both implementation and performance advantages. In this paper these conjectures are tested in the context of a CMOS gate array design and are found to be valid. This work was supported under an ARO grant.","PeriodicalId":424620,"journal":{"name":"1987 IEEE 8th Symposium on Computer Arithmetic (ARITH)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1987-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Implementation of the single modulus complex ALU\",\"authors\":\"R.-S. Kao, F. Taylor\",\"doi\":\"10.1109/ARITH.1987.6158703\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Recently the complex residue number system, or RNS, has been a subject of intense study. One special embodiment of this theory is the single modulus complex RNS processor which suggests both implementation and performance advantages. In this paper these conjectures are tested in the context of a CMOS gate array design and are found to be valid. This work was supported under an ARO grant.\",\"PeriodicalId\":424620,\"journal\":{\"name\":\"1987 IEEE 8th Symposium on Computer Arithmetic (ARITH)\",\"volume\":\"39 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1987-05-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1987 IEEE 8th Symposium on Computer Arithmetic (ARITH)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ARITH.1987.6158703\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1987 IEEE 8th Symposium on Computer Arithmetic (ARITH)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ARITH.1987.6158703","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Recently the complex residue number system, or RNS, has been a subject of intense study. One special embodiment of this theory is the single modulus complex RNS processor which suggests both implementation and performance advantages. In this paper these conjectures are tested in the context of a CMOS gate array design and are found to be valid. This work was supported under an ARO grant.
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