Data flow and buffer management in multi-channel data link controller

The paper discusses the data flow and buffer management for an integrated ASIC performing the high level data link control (HDLC) protocol processing functions for large number of multi-rate (n/spl times/64 kbps) and/or sub-rate (p/spl times/8 kbps) logical channels supported over time division multiplexing (TDM) network interfaces. The highly integrated ASICs are sought-out by the original equipment manufacturers (OEMs) to meet the growing demand for port and connection density. The integration, however, poses a significant challenge for ASIC developers in managing the large number of data flows. Thus, a data flow and buffer management mechanism is required for efficiently managing the data flows so as to maximize the utilization of the network bandwidth and minimize the data loss. The design and analysis of such a mechanism is addressed. The mechanism implementation encompasses both the host and ASIC domains, however, the host domain design is given emphasis in the paper. The critical parameters in the sub-system are identified and characterized utilizing the simulation model. A prototype is built for the host domain in the network driver interface specifications (NDIS) framework in the form of a kernel mode device driver on a generic computing platform. The mechanism was tested satisfactorily with the programmable ASIC device that consists of an embedded reduced instruction set computer (RISC) processor and many significant features suitable for TDM based telecommunications and data communications applications.