Yuki Ando, S. Shibata, S. Honda, H. Tomiyama, H. Takada
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Fast Design-Space Exploration Method for SW/HW Codesign on FPGAs
This paper presents an efficient design-space exploration method to identify the Pareto solution for the relation between the execution time and the hardware area. Initially, our method takes a particular system mapping that is surely in the Pareto solution, and then repeats the local search and the update of the Pareto solution until the Pareto solution reaches a steady state. Compared to genetic-algorithm-based methods, we found that our method outputs the Pareto solution with a smaller number of explorations for larger design spaces.
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