Single-chip 5.8GHz DSRC transceiver with dual-mode of ASK and Pi/4-QPSK

We have developed a fully integrated 0.25 mum SiGe-BiCMOS transceiver with a power amplifier (PA), transmit / receive switch (T/R SW), orthogonal modulator / demodulator, received signal strength indicator (RSSI), and phase locked loop (PLL) for Dedicated Short Range Communications (DSRC) mobile terminals with Amplifier Shift Keying (ASK) and Pi/4- shifted Quadrature Phase Shift Keying (Pi/4-QPSK) dual-mode modulation. Transmitter architecture is based on the sliding-IF topology using 4.6 GHz VCO and a 1/4 divider. Receiver architecture is based on the fixed-IF super-heterodyne. For image spurious rejection in the transmitter, a passive band elimination filter (BEF) comprised of a differential inductor is implemented. The 3.1mm x 2.97 mm die is packaged in 5.8 mm x 5.8 mm 48 pin- VQFN.