Performance Investigation and Optimization of 2-D Material based Double Gate Tunneling Field-Effect Transistor (DG-TFET)

The aggressive reduction of FET devices predicted in Moore's law has escorted us to an exponential decrease in device performance. Shifting from existing FET devices to Tunneling Field-Effect Transistor (TFET) has demonstrated higher performance while maintaining a significantly lower transistor gate size. It offers a steep subthreshold swing slope with a substantially lower leakage current, resulting in competitively lower power absorption from ordinary FETs. However, to increase the control over the TFET device even further, a slight variation in a design known as the Double Gate Tunneling Field-Effect Transistor (DG- TFET) is implicated. In this study, I have investigated and adjusted the performance of an N-type DG-TFET by altering several parameters such as device materials, high-k dielectric as oxide layers, and oxide thickness. In the end, Tungsten Ditelluride (WTe2) a 2-D material is used as the device material, while Niobium pentoxide (Nb2O5) is used as the high-k dielectric material according to the optimization process of the DG-TFET. The device has achieved a subthreshold swing of 18.37 mv/Dec and an Ion/Ioff of 1011. Finally, I have also conducted a comparative analysis between DG-TFET and a Single Gate Tunneling Field-Effect Transistor (SG-TFET) device with identical specifications.