High-density CMOS neural probe implementing a hierarchical addressing scheme for 1600 recording sites and 32 output channels

This paper presents the design, fabrication and characterization of CMOS-based neural probes with a densely-packed electrode array. A hierarchical addressing scheme is implemented in the system which allows to integrate up to 1600 recording sites (17×17 μm2) arranged in 50 blocks of 32 electrodes each along a 100-μm-wide and 10-mm-long probe shaft. The electrodes within each block have a vertical and horizontal pitch of 20 μm resulting in an electrode-to-electrode separation of 3 μm. Single recording sites as well as combinations of 2×2 adjacent electrodes forming a virtually larger recording site of reduced impedance can be read out via 32 parallel analog output channels. The system was designed and fabricated in a 0.18 μm CMOS technology followed by an in-house post-CMOS process used to realize the electrode metallization and define the probe geometry. System functionality for electrode selection was verified by activating individual blocks along the shaft and switching recording sites to specific output channels. Impedance characterization of the electrodes revealed absolute values of 2.2±0.3 MΩ and 550±50 kΩ at 1 kHz for individual Pt electrodes and 2×2 electrode combinations, respectively.