{"title":"分布式电力系统中快速、敏感、低压负载的电路考虑","authors":"A. Rozman, K.J. Fellhoelter","doi":"10.1109/APEC.1995.468958","DOIUrl":null,"url":null,"abstract":"Integrated circuits for next generation computer systems subject the power subsystem to extremely large and fast load step transients, with allowable peak voltage deviations of typically less than two percent. These requirements pose a difficult problem for board level designers and are one of the major drivers for distributed power architectures. In this paper, the problem of maintaining tight regulation throughout the transient is examined, and circuit techniques are presented for its solution.<<ETX>>","PeriodicalId":335367,"journal":{"name":"Proceedings of 1995 IEEE Applied Power Electronics Conference and Exposition - APEC'95","volume":"9 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"51","resultStr":"{\"title\":\"Circuit considerations for fast, sensitive, low-voltage loads in a distributed power system\",\"authors\":\"A. Rozman, K.J. Fellhoelter\",\"doi\":\"10.1109/APEC.1995.468958\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Integrated circuits for next generation computer systems subject the power subsystem to extremely large and fast load step transients, with allowable peak voltage deviations of typically less than two percent. These requirements pose a difficult problem for board level designers and are one of the major drivers for distributed power architectures. In this paper, the problem of maintaining tight regulation throughout the transient is examined, and circuit techniques are presented for its solution.<<ETX>>\",\"PeriodicalId\":335367,\"journal\":{\"name\":\"Proceedings of 1995 IEEE Applied Power Electronics Conference and Exposition - APEC'95\",\"volume\":\"9 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-03-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"51\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of 1995 IEEE Applied Power Electronics Conference and Exposition - APEC'95\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/APEC.1995.468958\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of 1995 IEEE Applied Power Electronics Conference and Exposition - APEC'95","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APEC.1995.468958","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Circuit considerations for fast, sensitive, low-voltage loads in a distributed power system
Integrated circuits for next generation computer systems subject the power subsystem to extremely large and fast load step transients, with allowable peak voltage deviations of typically less than two percent. These requirements pose a difficult problem for board level designers and are one of the major drivers for distributed power architectures. In this paper, the problem of maintaining tight regulation throughout the transient is examined, and circuit techniques are presented for its solution.<>
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