Yu Wang, Junhui Xiang, Xianliang Chen, Tao Yang, N. Yan, Hao Min
{"title":"用于低功耗物联网应用的全逻辑CMOS兼容非易失性存储器","authors":"Yu Wang, Junhui Xiang, Xianliang Chen, Tao Yang, N. Yan, Hao Min","doi":"10.1109/IOT.2015.7356553","DOIUrl":null,"url":null,"abstract":"This paper presents a 512-bit low power electrically programmable embedded non-volatile memory (eNVM) for the Internet of Things (IoT) applications. A novel memory bit cell which is fully compatible to the CMOS logic process is developed using dual tunneling gate structure. Costumer designed lateral double diffused MOS transistor (LDMOS) is proposed in a novel high voltage management circuit to improve the reliability and safety of the memory established by thin gate oxide transistors. In charge pump design, a frequency step-up scheme is proposed to control the current surge during writing operation, thus large voltage droops in the power supply is prevented, improving the stability of the system. The memory is implemented in a standard 0.13μm CMOS technology process. Measured results indicate that under the supply voltage of 1.2 V, it consumes 9.2 μW (22.9 μW) at the read (write) rate of 6.78 Mb/s (8 kb/s). Endurance characteristics under 100k program cycles stress test and data retention characteristics of up to 10 years are demonstrated.","PeriodicalId":251982,"journal":{"name":"2015 5th International Conference on the Internet of Things (IOT)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"A fully logic CMOS compatible non-volatile memory for low power IoT applications\",\"authors\":\"Yu Wang, Junhui Xiang, Xianliang Chen, Tao Yang, N. Yan, Hao Min\",\"doi\":\"10.1109/IOT.2015.7356553\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a 512-bit low power electrically programmable embedded non-volatile memory (eNVM) for the Internet of Things (IoT) applications. A novel memory bit cell which is fully compatible to the CMOS logic process is developed using dual tunneling gate structure. Costumer designed lateral double diffused MOS transistor (LDMOS) is proposed in a novel high voltage management circuit to improve the reliability and safety of the memory established by thin gate oxide transistors. In charge pump design, a frequency step-up scheme is proposed to control the current surge during writing operation, thus large voltage droops in the power supply is prevented, improving the stability of the system. The memory is implemented in a standard 0.13μm CMOS technology process. Measured results indicate that under the supply voltage of 1.2 V, it consumes 9.2 μW (22.9 μW) at the read (write) rate of 6.78 Mb/s (8 kb/s). Endurance characteristics under 100k program cycles stress test and data retention characteristics of up to 10 years are demonstrated.\",\"PeriodicalId\":251982,\"journal\":{\"name\":\"2015 5th International Conference on the Internet of Things (IOT)\",\"volume\":\"2 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-12-17\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 5th International Conference on the Internet of Things (IOT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IOT.2015.7356553\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 5th International Conference on the Internet of Things (IOT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IOT.2015.7356553","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A fully logic CMOS compatible non-volatile memory for low power IoT applications
This paper presents a 512-bit low power electrically programmable embedded non-volatile memory (eNVM) for the Internet of Things (IoT) applications. A novel memory bit cell which is fully compatible to the CMOS logic process is developed using dual tunneling gate structure. Costumer designed lateral double diffused MOS transistor (LDMOS) is proposed in a novel high voltage management circuit to improve the reliability and safety of the memory established by thin gate oxide transistors. In charge pump design, a frequency step-up scheme is proposed to control the current surge during writing operation, thus large voltage droops in the power supply is prevented, improving the stability of the system. The memory is implemented in a standard 0.13μm CMOS technology process. Measured results indicate that under the supply voltage of 1.2 V, it consumes 9.2 μW (22.9 μW) at the read (write) rate of 6.78 Mb/s (8 kb/s). Endurance characteristics under 100k program cycles stress test and data retention characteristics of up to 10 years are demonstrated.