Impact of gate-source/drain underlap and ground plane (GP) structures towards digital FoM of 25 nm UTBB SOI MOSFETs

This work investigates the impact of gate-source/drain underlap (LUL) together with different ground plane (GP) structures on the digital figure-of-merit (FoM) of 25 nm UTBB FDSOI devices using two-dimensional (2D) numerical simulations. It is found for all ground plane structure, longer underlap produces 1) lower off-current (Ioff) but at a cost of lower on-current (Ion), thus a lower transconductance (gm). In terms of the impact of different GP structures, longer underlap shows 1) stronger influence on the Id-Vg characteristics 2) an improvement in the DIBL as a result of lower effect of drain potential, compared with no-underlap. In addition, DIBL dependence on various GP structures is higher at shorter underlap as compared to longer underlap. It is shown that to achieve good Short-Channel Effects (SCEs) control and optimal digital results, careful design consideration need to be done in selecting a combination of LUL and GP structures to be adopted in the device design, as there is a trade-off between Ioff and Ion, as well as on the DIBL.