The Sub-Threshold Leakage Reduction Techniques in CMOS Circuits

Minimizing the leakage power has become one of the major concerns in low-voltage, low-power and high performance applications in VLSI involving CMOS circuits. The first part of this paper describes the need for low power and drawbacks in technology scaling and power components. The second part describes the various sources of leakage power and various techniques involved in reducing the same without affecting the performance. Various power reduction techniques can be employed at process and circuit level which includes Transistor stacking, Multiple threshold (MTCMOS), Dynamic threshold, Dual threshold, Variable threshold (VTCMOS), Pin-reordering, Supply voltage scaling & stacking techniques.