Design and Implementation of Vedic Multiplier using Carry Increment Adder

Vedic multiplier uses adders as its fundamental building block. One of the crucial performance criteria for many digital circuits is the circuit’s operating speed, which ultimately depends on the basic adder unit’s delay. This project is devoted to the construction and analysis of a speed Vedic multiplier that uses various adders to analyse speed, area, and power. Using the carry increment adder and Halfadders in Verilog HDL, a 16-bit Vedic multiplier is created. Modelsim is used to simulate the modules, while Xilinx ISE 14.7 is used to synthesise them. In this project, a carry increment adder-based Vedic multiplier will be implemented using the CLA, and its performance will be compared to Vedic multiplier implemented using the ripple carry adder.. In this project an implementation of Vedic Multiplier using carry increment adder and comparing it with the Vedic multiplier using Ripple Carry Adder will be performed. The synthesis report shows that CIA-CLA has 1% lesser area than Vedic Multiplier using Ripple Carry Adder and CIA-RCA. and CIA-CLA has 10% greater delay than Vedic Multiplier using Ripple Carry Adder and CIA-RCA.