Assertion and Coverage Driven Test Generation Tool for RTL Designs

RTL verification is still one the most challenging activities in digital system development as it is still the bottleneck in the time-to-market for an integrated circuit development cycle. Thus reducing verification time is one of the most important targets. In this paper, a tool is developed to generate automatic tests from SystemVerilog assertions or SystemVerilog Coverage. The proposed tool is tested using different memory modules starting from single port RAM through Multiple ports RAM, FIFO and the DDRx families. The performance, regarding the runtime, has been compared with the handcrafted test case generation process. Moreover, the performance has been compared with other automatic test generation tools. Results shows the effectiveness of the proposed design. The proposed tool excelled in terms of its run-time, complexity, and coverage percentage.