基于网络工作台的FPGA上Blokus Duo的人工智能

N. Sugimoto, Takaaki Miyajima, Takuya Kuhara, Y. Katuta, Takushi Mitsuichi, H. Amano
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引用次数: 1

摘要

本文提出了一种基于fpga的Blokus Duo求解器的设计。它使用带有α - β剪枝和移动排序的极大极小算法来搜索博弈树。此外,还使用名为CyberWorkBench (CWB)的HLS工具来实现硬件。通过使用CWB中的函数,可以生成并行的全流水线设计。实现的求解器工作在100MHz,使用Digilent Atlys板上的Xilinx Spartan-6 XC6SLX45 FPGA。在大多数情况下,它可以在移动三步后搜索状态。
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Artificial intelligence of Blokus Duo on FPGA using Cyber Work Bench
This paper presents a design of an FPGA-based Blokus Duo solver. It searches a game tree by using the miniMax algorithm with alpha-beta pruning and move ordering. In addition, HLS tool called CyberWorkBench (CWB) is used to implement hardware. By making the use of functions in CWB, parallel fully pipelined design is generated. The implemented solver works at 100MHz with Xilinx Spartan-6 XC6SLX45 FPGA on the Digilent Atlys board. It can search states after three moves in most cases.
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