{"title":"利用电流复用技术设计低功耗CMOS低噪声放大器","authors":"Hardik Sathwara, Kehul A. Shah","doi":"10.1109/NUICONE.2015.7449628","DOIUrl":null,"url":null,"abstract":"This paper presents a new LNA architecture comprise current reuse topology. The design is carried out in BSNIM3 180 nm CMOS technology. The proposed LNA consumes less power of 12.49 mW as compared to other existing architectures, while providing better gain (16.78 dB) and low NF i.e. less than 5 dB over the frequency range of 3 to 10 GHz. The design offers power gain (S21) of 7.5 dB and input return loss (S11) of -14 dB. All simulations are performed by using EDA Tanner T-Spice and ADS 2011.10 tools.","PeriodicalId":131332,"journal":{"name":"2015 5th Nirma University International Conference on Engineering (NUiCONE)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"Design of low power CMOS low noise amplifier using current reuse technique\",\"authors\":\"Hardik Sathwara, Kehul A. Shah\",\"doi\":\"10.1109/NUICONE.2015.7449628\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a new LNA architecture comprise current reuse topology. The design is carried out in BSNIM3 180 nm CMOS technology. The proposed LNA consumes less power of 12.49 mW as compared to other existing architectures, while providing better gain (16.78 dB) and low NF i.e. less than 5 dB over the frequency range of 3 to 10 GHz. The design offers power gain (S21) of 7.5 dB and input return loss (S11) of -14 dB. All simulations are performed by using EDA Tanner T-Spice and ADS 2011.10 tools.\",\"PeriodicalId\":131332,\"journal\":{\"name\":\"2015 5th Nirma University International Conference on Engineering (NUiCONE)\",\"volume\":\"31 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 5th Nirma University International Conference on Engineering (NUiCONE)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/NUICONE.2015.7449628\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 5th Nirma University International Conference on Engineering (NUiCONE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NUICONE.2015.7449628","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design of low power CMOS low noise amplifier using current reuse technique
This paper presents a new LNA architecture comprise current reuse topology. The design is carried out in BSNIM3 180 nm CMOS technology. The proposed LNA consumes less power of 12.49 mW as compared to other existing architectures, while providing better gain (16.78 dB) and low NF i.e. less than 5 dB over the frequency range of 3 to 10 GHz. The design offers power gain (S21) of 7.5 dB and input return loss (S11) of -14 dB. All simulations are performed by using EDA Tanner T-Spice and ADS 2011.10 tools.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
