SRT除法和平方根的新算法和VLSI架构

S. E. McQuillan, J. McCanny, R. Hamill
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引用次数: 45

摘要

提出了SRT除法和平方根的两种根号算法。对于这些方案,结果数和残差同时计算,相邻行的计算是重叠的。因此,它们的性能应该超过基数为2的SRT方法。本文还介绍了用于实现新的除法和平方根方法的VLSI阵列结构。
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New algorithms and VLSI architectures for SRT division and square root
Radix two algorithms for SRT division and square-rooting are developed. For these schemes, the result digits and the residuals are computed concurrently and the computations in adjacent rows are overlapped. Consequently, their performance should exceed that of the radix 2 SRT methods. VLSI array architectures for implementing the new division and square-rooting methods are also presented.<>
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Hardware starting approximation for the square root operation A modular multiplication algorithm with triangle additions Division with speculation of quotient digits Design of a fast validated dot product operation Exact rounding of certain elementary functions
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