{"title":"在嵌入式系统中防止内存窥探的缓存锁定和加密","authors":"Jason DeJesus, J. Chandy","doi":"10.1109/DSC54232.2022.9888802","DOIUrl":null,"url":null,"abstract":"Embedded systems are designed to have security measures in place that protect users' data from software and network attacks, but these measures can prove useless when the attacker gains physical access to the system. Research has shown that dynamic random access memory (DRAM) is vulnerable to attacks that take advantage of its remanence property where data remains in DRAM shortly after the system is powered off. In this paper, we propose a method utilizing both cache locking and encryption to secure the DRAM on any embedded system by modifying the cache architecture of the CPU. We demonstrate an implementation using a MicroBlaze CPU, but the design can be used with any FPGA soft-core CPU, even if it does not have pre-existing cache locking capabilities. The cache modifications introduce almost no impact on performance and minimal extra hardware utilization.","PeriodicalId":368903,"journal":{"name":"2022 IEEE Conference on Dependable and Secure Computing (DSC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Cache Locking and Encryption to Prevent Memory Snooping in Embedded Systems\",\"authors\":\"Jason DeJesus, J. Chandy\",\"doi\":\"10.1109/DSC54232.2022.9888802\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Embedded systems are designed to have security measures in place that protect users' data from software and network attacks, but these measures can prove useless when the attacker gains physical access to the system. Research has shown that dynamic random access memory (DRAM) is vulnerable to attacks that take advantage of its remanence property where data remains in DRAM shortly after the system is powered off. In this paper, we propose a method utilizing both cache locking and encryption to secure the DRAM on any embedded system by modifying the cache architecture of the CPU. We demonstrate an implementation using a MicroBlaze CPU, but the design can be used with any FPGA soft-core CPU, even if it does not have pre-existing cache locking capabilities. The cache modifications introduce almost no impact on performance and minimal extra hardware utilization.\",\"PeriodicalId\":368903,\"journal\":{\"name\":\"2022 IEEE Conference on Dependable and Secure Computing (DSC)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-06-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 IEEE Conference on Dependable and Secure Computing (DSC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DSC54232.2022.9888802\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE Conference on Dependable and Secure Computing (DSC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DSC54232.2022.9888802","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Cache Locking and Encryption to Prevent Memory Snooping in Embedded Systems
Embedded systems are designed to have security measures in place that protect users' data from software and network attacks, but these measures can prove useless when the attacker gains physical access to the system. Research has shown that dynamic random access memory (DRAM) is vulnerable to attacks that take advantage of its remanence property where data remains in DRAM shortly after the system is powered off. In this paper, we propose a method utilizing both cache locking and encryption to secure the DRAM on any embedded system by modifying the cache architecture of the CPU. We demonstrate an implementation using a MicroBlaze CPU, but the design can be used with any FPGA soft-core CPU, even if it does not have pre-existing cache locking capabilities. The cache modifications introduce almost no impact on performance and minimal extra hardware utilization.