{"title":"AMD Opteron™CMP北桥架构:现在和未来","authors":"Patrick Conway, B. Hughes","doi":"10.1109/HOTCHIPS.2006.7477747","DOIUrl":null,"url":null,"abstract":"This article consists of a collection of slides from the author's conference presentation on AMD's Opteron, the company's dual-core 64-bit x86 processor. Some of the specific topics discussed include: the features and system specifications of Opteron; memory management facilities; a comparison of previous and current system architectures; the BorthBridge command processing flow architecture; and planned next generation of processor technologies.","PeriodicalId":302249,"journal":{"name":"2006 IEEE Hot Chips 18 Symposium (HCS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"The AMD Opteron™ CMP NorthBridge architecture: Now and in the future\",\"authors\":\"Patrick Conway, B. Hughes\",\"doi\":\"10.1109/HOTCHIPS.2006.7477747\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This article consists of a collection of slides from the author's conference presentation on AMD's Opteron, the company's dual-core 64-bit x86 processor. Some of the specific topics discussed include: the features and system specifications of Opteron; memory management facilities; a comparison of previous and current system architectures; the BorthBridge command processing flow architecture; and planned next generation of processor technologies.\",\"PeriodicalId\":302249,\"journal\":{\"name\":\"2006 IEEE Hot Chips 18 Symposium (HCS)\",\"volume\":\"15 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-08-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 IEEE Hot Chips 18 Symposium (HCS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/HOTCHIPS.2006.7477747\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 IEEE Hot Chips 18 Symposium (HCS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/HOTCHIPS.2006.7477747","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The AMD Opteron™ CMP NorthBridge architecture: Now and in the future
This article consists of a collection of slides from the author's conference presentation on AMD's Opteron, the company's dual-core 64-bit x86 processor. Some of the specific topics discussed include: the features and system specifications of Opteron; memory management facilities; a comparison of previous and current system architectures; the BorthBridge command processing flow architecture; and planned next generation of processor technologies.
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