Distributed arithmetic in the design of high speed hardware fuzzy inference systems

This paper presents an approach for implementing center average defuzzifier by means of distributed arithmetic. This approach was applied in the design of two digital fuzzy processors, their architectures are described and compared in terms of system level organization. An automatic hardware code generation tool was used for specifying these fuzzy processors. Furthermore, they were implemented over a VirtexE/spl reg/ FPGA. Implementation results show that it is possible to obtain a processing speed up to 45 MFLIPS and reduced area cost for distributed arithmetic based parallel organized fuzzy inference systems.