Experiences with modeling memory contention for multi-core industrial real-time systems

Wide availability of multicore CPUs makes concurrency a critical design factor for the software architecture and execution models of industrial controllers, especially with messages passing between tasks running on different cores. To improve performance, we refactored a standardized shared memory IPC mechanism implemented with traditional kernel locks to use lock-free algorithms. Prototyping the changes made it possible to determine the speed-up when the locks were removed, but we could neither easily confirm whether the IPC performance would suffice for the communication patterns in our real-time system, nor could we tell how well the implementation would scale to CPUs with more cores than our test machine. In this paper we report on our experience with using a queuing petri net performance model to predict the impact of memory contention in a multi-core CPU on architecture level performance. We instantiated our model with benchmark data and prototype measurements. The results from our model simulation provide valuable feedback for design decisions and point at potential bottlenecks. Comparison of the prototype's performance with our model simulation results increases credibility of our work. This paper supports other practitioners who consider applying performance modeling to quantify the quality of their architectures.