{"title":"高速自启动通用电压电平移位器","authors":"Mahesh Vaidya, Alok Naugarhiya, Shrish Verma","doi":"10.1109/ICAECC.2018.8479461","DOIUrl":null,"url":null,"abstract":"Usage of two separate Positive and Negative voltage level shifter on the System-on-chip, increase the area and the complexity of the circuit. In the conventional circuit of both type of level shifter contention of crowbar current is present. That will affect the performance parameter like propagation delay due to slow switching and increase in power dissipation due to leakage current. To avoid the separate use of the circuit and effective performance of the circuit we have proposed the generic voltage level shifter design. This design will be able to produce both the output simultaneously. The propagation delay is observed 12.18ns and 12.82ns for positive and negative voltage shifter respectively. The Dynamic Power Dissipation has been observed 8.25 µW for 1.2V at 0.5MHz frequency. The simulation has been done in Cadence using 45nm gpdk.","PeriodicalId":106991,"journal":{"name":"2018 Second International Conference on Advances in Electronics, Computers and Communications (ICAECC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"High Speed Bootstrapping Generic Voltage Level Shifter\",\"authors\":\"Mahesh Vaidya, Alok Naugarhiya, Shrish Verma\",\"doi\":\"10.1109/ICAECC.2018.8479461\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Usage of two separate Positive and Negative voltage level shifter on the System-on-chip, increase the area and the complexity of the circuit. In the conventional circuit of both type of level shifter contention of crowbar current is present. That will affect the performance parameter like propagation delay due to slow switching and increase in power dissipation due to leakage current. To avoid the separate use of the circuit and effective performance of the circuit we have proposed the generic voltage level shifter design. This design will be able to produce both the output simultaneously. The propagation delay is observed 12.18ns and 12.82ns for positive and negative voltage shifter respectively. The Dynamic Power Dissipation has been observed 8.25 µW for 1.2V at 0.5MHz frequency. The simulation has been done in Cadence using 45nm gpdk.\",\"PeriodicalId\":106991,\"journal\":{\"name\":\"2018 Second International Conference on Advances in Electronics, Computers and Communications (ICAECC)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-02-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 Second International Conference on Advances in Electronics, Computers and Communications (ICAECC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICAECC.2018.8479461\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 Second International Conference on Advances in Electronics, Computers and Communications (ICAECC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICAECC.2018.8479461","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
High Speed Bootstrapping Generic Voltage Level Shifter
Usage of two separate Positive and Negative voltage level shifter on the System-on-chip, increase the area and the complexity of the circuit. In the conventional circuit of both type of level shifter contention of crowbar current is present. That will affect the performance parameter like propagation delay due to slow switching and increase in power dissipation due to leakage current. To avoid the separate use of the circuit and effective performance of the circuit we have proposed the generic voltage level shifter design. This design will be able to produce both the output simultaneously. The propagation delay is observed 12.18ns and 12.82ns for positive and negative voltage shifter respectively. The Dynamic Power Dissipation has been observed 8.25 µW for 1.2V at 0.5MHz frequency. The simulation has been done in Cadence using 45nm gpdk.