A 50 GHz 2 mW Inductor-Less Frequency Divider with Back-Gate Tuning Achieving a Locking Range of 160% in 22 FDSOI

This work presents a divide-by-2 frequency divider designed using 22-nm CMOS Fully-Depleted Silicon on Insulator (FDSOI) technology. The circuit combines a dynamic load modulation, current reuse technique and back gate tuning to obtain a division range of 10 to 92 GHz with 0dBm input signal to the divider core (due to measurement limitations measured range is 20 to 60 GHz). The divider is suitable for all 5G bands, WiGiG, E-band radar and others and operates from a CMOS rail with no AC coupling required. The divider consumes less than 2 mW from 1V supply to obtain a figure-of-merit of more than 39 GHz/mW and occupies less than 65 um2 of silicon area.