Modelling and Analysis of different types of TSV for Three Dimensional Integrated Circuits

The majority of systems on the market today are made up of intricate SoCs with integrated processors, large quantities of memory and FPGAs, but they do not offer a complete system solution for real-world systems [1]. Designers are faced with numerous technological and financial obstacles when attempting to combine such different technologies onto a single chip [2]. Additionally, vertical integration was shown to be a desirable alternative due to the continuously growing needs for low cost, smaller chips with more capability, and shorter time to market for portable systems [3]. Three-dimensional integration is the vertical interconnection of unpackaged or packaged semiconductors [3]. The most promising technique for designing ICs and systems with high performance, functionality, and lower power consumption than the 2D technologies is three dimensional integrated circuits (IC) in the form of three-dimensionally stacked chips. Using inter-tier interconnects that directly cross the substrate, various dice can be joined in 3D integration [4]. This is referred as Through Silicon Via (TSV) based 3D integration technology. To provide uniform environmental conditions throughout all tiers, TSV tapering is done to achieve the least amount of voltage drop and delay difference possible. When the resistance values and current demand for each tier are known, thevenin network architecture may be used for TSV sizing.