Codec Implementation of QC-LDPC Code in CCSDS Near-Earth Standard

Recently, type-II quasi-cyclic (QC) low-density parity-check (LDPC) codes have attracted increasing attention due to their compact structures and promising decoding performance. In this paper, the type-II QC-LDPC code standardized for use in near-earth application is implemented by FPGA. On the basis of analysis for the generator matrix and parity-check matrix of the code, the codec for the type-II LDPC code is designed. By using an XC4VLX200-FPGA, the maximum clock frequency of the encoder is 287MHz at the cost of 810 slices and 15 Blockrams, while the maximum clock frequency of the decoder is 244 MHz at the cost of 10481 slices and 74 Blockrams. The testing result for the codec performance shows that such a code can completely satisfy the requirement for on-board channel coding application. The codec developed in this paper has been successfully employed in many remote-sensing satellite missions in China.