System level power consumption modeling and optimization for coarse-grained reconfigurable architectures

Coarse Grained Reconfigurable Architectures (CGRAs) are promising platform because of its high performance and low cost. With the popularization of CGRAs, low power design has become one of the most challenging tasks to concern. This paper presents an improved instruction level power estimation model at the system-level as a platform for power optimization. With this model, we adopt a modified resource-monitoring heuristic on instruction level to reduce power consumption. Experiment shows our proposed approach could reduce the power by 22.9% on average with only 3.9% decreasing performance.