On The Efficiency of Heterogeneous System Architecture for Image Processing

Graphics Processing Unit (GPU) based image processing algorithms have been previously developed to take advantage of the highly parallel nature of GPUs. However, these algorithms still exhibit problems of high programming complexity, relatively low device utilisation and difficulty when integrating into larger systems. In this paper, a set of image processing modules have been developed to take advantage of the computational characteristics of a System on a Chip (SoC) that contains both a GPU and a Central Processing Unit with fine grained shared virtual memory capabilities. The usage of shared memory simplifies design and removes the latency and bandwidth constraints associated with discrete GPUs on the Peripheral Component Interconnect Express (PCIe) bus. These modules feature a simple, composite design that improves upon previously developed algorithms by running discrete stages of the algorithms on the portions of the SoC that are best suited for them. This allows greater efficiency and lower code complexity than more expensive discrete-GPU-based alternatives.